The increasing demands for bandwidth resulting from the ubiquitous deployment of the internet and multimedia applications have generated the need for faster, more efficient networks and network switches, principally, packet switches. There are at least three common switching architectures used in packet switches for forwarding data packets from input ports to output ports: crosspoint (also known as crossbar) matrix, shared bus, and shared memory. A crossbar matrix essentially creates a transient “circuit” between two ports for the duration of a data packet (or subset of a data packet) exchange, based on the destination address and/or other information within a data packet acquired by the packet's entry port. Latency through the switch is minimal since the entire data packet need not be stored within the switch in the process of forwarding the packet. A drawback of the crossbar matrix architecture is the head-of-line blocking that occurs when more than one entry port attempts to send data to the same exit port. A shared-bus architecture uses a common bus as the exchange mechanism for data packets between ports. Depending on the design, each input and output port (or small group of ports) can have its own memory. Like the crossbar matrix, the shared bus architecture is subject to blocking at busy ports.
A shared memory architecture uses a single common memory as the exchange mechanism for data packets between ports. All ports access the shared memory via a shared memory bus. An arbitration mechanism, such as time division multiplexing, controls port access to the memory ensuring each entry port a chance to store received data that can then be accessed by the exit port. A problem with present shared memory architectures, however, is that they are not fast enough to transfer multiple gigabits of data per second from one port to another without blocking port access to memory. Such transfer rates are required for newer, extremely fast packet switches for use in local area networks (LANs), wide area networks (WANs), and telephony and other kinds of switching systems.
Accordingly, there is a need for an improved shared memory architecture for a switching device that can transport data through the switch at the extremely high data rates required to keep up with the newer networks.